In the present era of very large scale integrated (VLSI) circuits, there has been a trend toward shrinking the dimensions of transistors and other semiconductor structures to facilitate greater packing densities. With this shrinkage and denser packing of semiconductor devices, substrate leakage currents and device interactions have become a concern which require some form of isolation between devices.
A number of approaches has been proposed to provide this isolation. For example, U.S. Pat. No. 3,979,237, issued to Marcom et al, discloses a method of forming grooves in a semiconductor body, coating the grooves with an insulating layer, refilling the grooves with a silicon material, and then planarizing the top of the refilled grooves to ensure that the top of the silicon areas is planar. As a result, there are provided insulated grooves filled with semiconductor material.
A recent technology which appears to be particularly promising in providing greater isolation is that of a silicon-on-insulator (SOI) approach. For example, IBM Technical Disclosure Bulletin, Volume 24, No. 9, Feb. 1982, authored by Chu, Tsang, and Joy, discloses a method whereby isolated silicon regions are embedded in indentations in a dielectric substrate. Similarly, IBM Technical Disclosure Bulletin, Volume 27, No. 8, January 1985, authored by Silvestri, discloses a method of forming fully isolated epitaxial silicon growth regions on an insulator, which are then used to facilitate the construction of fully isolated FET, Bipolar, and MOSFET integrated circuits. Often in achieving the desired SOI structure, bonding methods are applied to fuse one silicon wafer to a second "Handle" wafer. Examples of these bonding methods can be seen in Laskey, "Wafer Bonding for Silicon-On-Insulator Technologies", Appl. Phys. Lett., 48(1), 6 January 1986; and Laskey, Stiffer, White, Abernathey, "Silicon-On-Insulator (SOI) By Bonding and Etch-Back", IEDM 28.4, Dec. 1-4 1985.
One type of silicon-on-insulator construction with which the present invention is concerned is illustrated in, and will be described with reference to, FIGS. 1A and 1B. In FIG. 1A, a thin silicon layer 104 is on top of a thin insulator 102. The insulator layer 102 can be formed of any insulating material, and typically is silicon dioxide. Mechanical support and integrity are also provided by formation on a support body 100, which is typically a silicon wafer.
In FIG. 1B, the silicon-on-insulator layer of FIG. 1A has been masked, etched, and otherwise processed to provide isolated devices 110, 112, 114, and 116 formed on silicon islands 120, 122, 124, and 126, respectively. These silicon islands can be doped or otherwise treated to fabricate any of a multitude of semiconductor devices, for example, FET amplifiers, bipolar amplifiers, MOSFETs, etc. Note that the devices are totally isolated from one another, thereby preventing stray substrate leakage currents, and also preventing undesirable interactions between devices.
Also, note that the height of the device 112 is different from the height of devices 110, 114 and 116. This non-uniformity is due to the localized planar non-uniformity 106 indicated in FIG. 1A. As the device 112 has a shorter silicon island 122 than the silicon islands 120, 124 and 126 of the devices 110, 114, and 116, respectively, the device 112 effectively has a smaller silicon substrate area which produces a device 112 having operational parameters different from those of the devices 110, 114, and 116. In order to facilitate construction of semiconductor devices having substantially the same operational parameters, it would be desirable to have an SOI layer which has a planar top surface and is of uniform thickness.
It is also desirable to have an SOI layer with a planar top surface and a body of uniform thickness for several other reasons. First, projected photomask exposures may be slightly out of focus at localized planar non-uniformities. Second, if the tops of the resultant devices are planar, metalization wiring structure mask tolerances are somewhat relieved, and etch times to form stud-down structures to connect to the devices can be more accurately predicted.
FIG. 2A illustrates a silicon-on-insulator (SOI) having the desired characteristics of a planar top surface and a body of uniform thickness. In particular, a silicon layer 204 is on top of the insulator layer 102 which, in turn, is provided on top of the support body 100. In FIG. 2B, the silicon-on-insulator layer of FIG. 2A has been masked, etched, and otherwise processed to provide isolated devices 210, 212, 214 and 216 constructed on uniform silicon islands 220, 222, 224, and 226, respectively. Since the silicon islands 220, 222, 224, and 226 are uniform in thickness, the devices 210, 212, 214 and 216, respectively, have substantially similar operating parameters. Also, as the tops of the resultant devices are substantially planar, tolerance requirements in the end of the line processing to add a metalization wiring structure will be somewhat relaxed.
One prior art teaching which has achieved excellent results in producing a substantially uniform and planar SOI layer is that of U.S. Pat. No. 4,601,779, assigned to the present assignee, and issued to Abernathey et al. The resultant SOI structures by Abernathey et al serve as a preferred starting structure for the present invention, and as such, the teachings of Abernathey et al are incorporated herein by reference. However, there exists a need for a method which produces still greater planarity and thickness uniformity for silicon-on-insulator layers.